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| tss902e 1 mhs rev. d april 1999 1. description digital communication channels are inherently noisy, making transmission error control essential for reliable communication at low transmit power. the temic tss902e is a singlechip forward error correction decoder; it conforms to the mpegii transport layer protocol specified by iso/iec standard and fec requirements of digital video broadcasting (dvb) specification; its typical applications are dvb satellites, regenerative multimedia transmission satellites and military communications. the temic tss902e capabilities rely on viterbi and reedsolomon decoding algorithms to achieve extremely low biterror rate (ber) on the transmitted data. allowing discontinuous data blocks transmission, the tss902e burst mode feature is unique. the component is made of the following blocks: the inner decoder which performs the first level error detection and correction. this unit is made of a depuncturing block, a viterbi decoder (k=7) and a synchronization/clock controller. the convolutional deinterleaver, l=12 bytes for rs (204, 188, t=8) configuration. the outer decoder performs the second level error protection, using a reed solomon (255, 239) error correcting process. the descrambler for energy dispersal removal. a microprocessor interface to setup the device and monitor the testability functions. while monitoring the inner viterbi decoder ber output, the phase and the depuncturing pattern are tuned until the viterbi decoder proper alignment is found. the viterbi decoder output feeds the deinterleaver and reedsolomon decoder synchronization module. once the synchronization words have been found, the deinterleaver, the outer reedsolomon decoder and the descrambler are properly aligned. each functional block may be bypassed, giving more flexibility to a system designer. 2. features 2.1. general compliant with ets 300 421 for dvb, dvbs. compliant with iso/ieccd 138181 mpegii transport layer protocol. input code rate frequency up to 10 mbits/sec at 5v. onchip bit error rate monitoring. seu immunity better than 30 mev/mg/cm 2 total dose better than 50 krad (si). supply voltage 3 to 5v. power consumption 1w at 5v / 10mhz external clock frequency (code rate 7/8). 0.6 m m drawn cmos, 3 metal layers. 132pin mqfp. 2.2. viterbi decoder selectable code rates 1 / 2 , 2 / 3 , 3 / 4 , 5 / 6 and 7 / 8 or automatic acquisition mode . hard decision or 3bit softdecision decoder inputs. constraint length k = 7. e b /n 0 for ber 2.10 4 (code rate 1 / 2 ) 3.5 db. 2.3. synchronization controller automatic synchronization capabilities for qpsk or bpsk. responds to inverted synchronization byte. programmable synchronization byte. 2.4. convolutional deinterleaver error protected frame length n = 204. interleave depth i = 12. 2.5. reed solomon decoder supported programmable shortened code length k = 34 to 239, t = 8. correction capability up to t = 8 bytes. 2.6. descrambler (energy dispersal) polynomial generator q(x) = x 15 + x 14 + 1. mpegii inverted synchronization byte. viterbi and reedsolomon fec decoder
tss902e 2 mhs rev. d april 1999 3. term definitions table 1: viterbi term name definition range k encoding constraint length number of input bits contributing to the convolutional code. 7 traceback depth length of path through the trellis over which the viterbi decoder computes a decoded bit value likelihood. puncturing transmission rate increasing process. done by erasing some specific code bits before data transmission. code rate convolutional code input to output bits ratio. 2/3, 3/4, 5/6, 7/8 table 2: convolutional deinterleaver term name definition range i interleaving depth interleaved stream separation. 12 table 3: reedsolomon term name definition range k message length number of user data symbols in one message block. 34 k 239 bytes r check symbols symbols appended to the user data to detect errors. 16 bytes n codeword length sum of message and check symbols. n = k + r 50 n 255 bytes t error corrections maximum number of error corrections performed by the rs decoder. 8 tss902e 3 mhs rev. d april 1999 4. functional description this section describes the tss902e device architecture and its constituents functionality. pll depuncturing viterbi decoder deinterleaver reed solomon dec. descrambler microcontroller interface & test synchro. control dup[7:0] ad[7:0] resetb testxxx iext[2:0] qext[2:0] dataout[7:0] as cs irq rdwrb burstsyncin frameout syncout serial burstsyncout dataouts ckbitout ckoctout xxxoutf to external filter ckbitext figure 1: tss902e block diagram 4.1. synchronization the synchronization control block is made of two parts called synchrobit and synchroframe which algorithms are described hereafter. 4.1.1. the synchrobit module the synchrobit module performs the depuncturing block and the viterbi decoder synchronization by monitoring the bit error rate ( ber ). the viterbi ber calculation is done by the device during the averaging period whereas the monitoring period can be defined by the user in order to perform offline statistical ber calculations. the depuncturing module adds missing bits according to the code rate. since the code rate may be unknown, the depuncturing block may initially use a bad rate if the automatic mode has been selected (see rxvitcontrol register a/m and fre bits). furthermore, the depuncturing process may be uncorrectly synchronized although using the right code rate. both conditions will lead to an unsatisfactory ber value. the viterbi ber value is considered to be acceptable when it remains under the rxvitthreshold register value. this register is actually made of several registers, each associated to one code rate value (1/2, 2/3, 3/4, 5/6 and 7/8). if throughout the averaging period the ber value stays below the threshold, the synchrobit block sets the sbf (synchro bit found) flag within the rxvitstatus register, locks the pll and allows the synchroframe module to start the synchro word search. if, on the other hand, in automatic mode, the viterbi decoder ber value exceeds its programmed threshold during the averaging period, the device will enter in syncbit search mode trying to resolve at first the input data phase ambiguity within the current code rate; if the ber value still is too high, the device will assume that the depuncturing process tss902e 4 mhs rev. d april 1999 was not performed on the right input bits (the bits assumed to be missing were not on the right position) and the depuncturing statemachine will enter next state; finally, if the ber value still remains unacceptable, the code rate value will be changed and the device will restart the overall search process. warning : if the programmed threshold value is too high, the bit synchronization may be found on a wrong position. in automatic mode, all the threshold registers must be properly programmed according to the expected noise and code rate. in semiautomatic mode, the user can just define the right value in the known code rate threshold register. in manual mode, the maximum threshold value can be programmed in the code rate threshold register; the use of fre bit allows to find the bit synchronization for this code rate. (cf rxvitcontrol register usage) a loss of synchronization restarts a search of frame synchro. the data processing of blocks placed after syncframe block is restarted as well. the synchrobit module can be bypassed by bit sybe of the rxrsvitact register. when set, the sybe bit enables the synchronization between depuncturing and viterbi blocks; when cleared, the synchrobit module still maintains the sbf generation in order to allow other blocks to work; in this case the depuncturing rate is fixed (rate = 1/2, no phase ambiguity). 4.1.2. the synchroframe module starting on successful synchrobit process completion, the synchro_frame process waits for the frame synchronization word (47h) or the transport packet one (b8h) by default. the sync words search duration is limited by a timeout value defined through the rxsyncwctl register tov bits and rxvitsynccompword register scw bits. an unsuccessful sync words search produces an interrupt and sets the rxvitrsint0 register tio flag. whenever either sync word or bitwise inverted sync word is found, a counter is incremented and compared to the number of consecutive sync words at the expected position required to get synchronized ( rxsyncwctl register sy2/sy1/sy0 bits). the synchroframe process remains in the sync word waiting loop until the expected number of consecutive sync words is reached, then the synchroframe block sets the rxvitstatus register lck bit ( synchroframe locked). the default sync word value is 47h but it may be changed to any value through the rxsyncword register. the sync condition may take into account the bitwise inverted sync word search or not ( rxvitsynccompword register cena bit). the bitwise inverted sync word occurs every 8 frames by default but this value may be changed from 1 to 15 ( rxvitsynccompword register scw3 to scw0 bits). a maximum number of allowed mismatching bits can be defined when expecting the sync word ( rxsyncwctl register msy bits). the synchroframe process may restart under the following external conditions: a general reset is applied to the device. the synchro_frame module receives a restart signal from the synchrobit block. the bit synchronization is lost. the reedsolomon decoder is out of sync ( rxdesyncwctl register drsm bit); this condition may be masked. the descrambler module is out of sync ( rxdesyncwctl register dscm bit); this condition may be masked. the synchroframe module will lose sync again after lock, when the sync word is not found at the expected position for a number of consecutive frames which is specified in rxvitdesyncwctl register dsy[2:0] . the maximum number of mismatching bits for a missed sync word is programmable ( rxvitdesyncwctl register mds[1:0] bits). a loss of synchronization restarts a search of frame synchro. the data processing of blocks placed after syncframe block is restarted as well. the synchroframe module can be bypassed by bit sye of the rxrsvitact register. tss902e 5 mhs rev. d april 1999 4.2. depuncturing the puncturing process is a way to change the code rate. within a certain interval of code bits, some specific bits are simply not transmitted, i.e. erased. the depuncturing block must add these erased bits according to the transmission rate. this rate can be programmed in the rxvitrate register or automatically looked for by the synchro_bit module. the ets 300 421 (digital brodcasting systems for television, sound and data services; framing structure, channel cading and modulation for 11/12 ghz satellite services) defines punctured codes as in table 1. table 4: punctured code definition original coding code rates k g1 (x) g2 (y) 1/2 2/3 3/4 5/6 7/8 p dfree p dfree p dfree p dfree p dfree x:1 x:10 x:101 x:10101 x:1000101 y:1 y:11 y:110 y:11010 y:1111010 10 6 5 4 3 7 171 133 10 6 5 4 3 7 171 oct 133 oct i=x 1 i=x 1 y 2 y 3 i=x 1 y 2 i=x 1 y 2 y 4 i=x 1 y 2 y 4 y 6 q=y 1 q=y 1 x 3 y 4 q=y 1 x 3 q=y 1 x 3 x 5 q=y 1 y 3 x 5 y 7 depunctured add bit no bit x 2 x 4 x 2 y 3 x 2 y 3 x 4 y 5 x 2 x 3 x 4 y 5 x 6 y 7 note 1 = transmitted bit 0 = no transmitted bit for example, running with the 7/8 rate, the iext and qext inputs receive the following sequence: iext = a1, b2, b4, b6 qext = b1, b3, a5, a7 at a coding rate of 7/8, the device has to generate 6 bitsat the proper position when it reads 8 bits in order to obtain 14 bits (i.e. 7 symbols). depuncturing the above sequence gives: iext = a1, 1 , 1 , 1 , a5, 1, a7 qext = b1, b2, b3, b4, 1 , b6, 1 if the code rate is known, the viterbi decoder module may be set to work in manual mode (see the rxvitcontrol register, a/m and fre bits); in that case, the code rate must be defined through the rxvitrate register. if the code rate is unknown, the synchrobit module can retrieve it by cycling through the 1/2, 2/3, 3/4, 5/6 and 7/8 code rates, looking for a valid pattern; the synchrobit module may also consider a possible phase ambiguity or a depuncturing process error (the bits assumed to be missing were not at the right position). the depuncturing block can work in bpsk or qpsk modes (i and q information being serial on iext input in bpsk mode, therefore the internal bit clock frequency is half the external one). the depuncturing module can be bypassed by bit dpe of the rxrsvitact register. tss902e 6 mhs rev. d april 1999 4.3. viterbi decoder the viterbi decoder reads data from the depuncturing module i and q outputs and produces decoded bit information. the viterbi block i[2:0] and q[2:0] inputs may be configured to work in softdecision or harddecision mode by programming the rxvitcontrol register h/s bit. in softdecision mode, the 3bit input words are compared to seven thresholds. in harddecision mode, only the iext and qext most significant bits are used; other bits are ignored. the viterbi decoder can be bypassed by the rxrsvitact register ve bit. the viterbi decoder latency is 290 ckbitrate clock periods. ckbitrate is internally generated; its period is: where text is the ckbitext clock period. for instance, if text value is 100ns and rate is 3/4, t value is 67ns. latency = 19.5us the viterbi module can be bypassed by bit ve of the rxrsvitact register. 4.4. deinterleaver this part describes the process of convolutional deinterleaver as it is defined into ets 300 421 . this device allows the error burst at the output of the inner decoder to be randomized on a byte basis in order to improve the burst error correction capability of the outer decoder (reedsolomon). the principle of the interleaver is the following one : the interleaver is composed of i = 12 branches, cyclically connected to the input bytestream by the input switch. each branch is a firstin, fistout (fifo) shift register, with depth m*j cells (where m = 17 = n/i, n = 204 = error protected frame length, i = 12 = interleaving depth, j = branch index). for synchronization purpose, the sync bytes (47h) and the inverted sync bytes (b8h) will always be routed in the branch o0o of the interleaver (corresponding to a null delay) the deinterleaver process is similar except that the branch indexes are inverted (i.e. j = 0 corresponds to the largest delay). the deinterleaver synchronization can be carried out by routing the first recognized sync byte in the o0o branch. the deinterleaver can be bypassed by bit die of the rxrsvitact register. 4.5. reedsolomon decoder the inner code has to be an 8errorcorrecting reedsolomon code over gf(2.8) (galois field). the natural length of this code is 255 symbols and since it can correct up to 8 errors, the code has 16 check symbols. this rs8 code can be shortened by any number of symbols resulting in a code length n, 50 tss902e 8 mhs rev. d april 1999 4.7.6. viterbi decoding burst mode constraints patent pending. 4.7.7. synchrobit burst mode constraints the synchro-bit block can also be used during burst mode operation. however the errors issued from the viterbi decoder will be taken into account only when they are recognized as being part of valid data. since the synchro-frame process will start only after the synchro-bit is locked, the synchronization packets must be long enough to remove any ambiguity. 4.7.8. synchroframe burst mode constraints in addition to the frame synchronization process, the synchroframe block organizes the viterbi data output as bytes. when operating in burst mode, this serial to parallel conversion is the only useful operation, since the reedsolomon decoder uses the bytes and synchroframe signal syncout to perform its decoding. the synchroframe block constraint is to have packets being multiple of 8 bits and an inter-burst of at least 7 bits. the p ambiguity removal at the synchro-frame level can be done by software. the synchro frame signal syncout delimits the first generated byte and is regenerated at the beginning of each new frame. the frame length is defined in the rxrsframel register, thus allowing to determine the beginning of each new frame. tss902e 9 mhs rev. d april 1999 4.8. global synchronization before starting data process the pll must be locked. according to the input clock bit frequency, it can be necessary to program the rxvitfreqin register. the received data are first processed by the depuncturing block, no matter their value. then, the depunctured data go to viterbi decoder. viterbi counts the errors found in this data stream. the synchrobit block is in charge of collecting the error number over a programmable averaging period ( rxvitsearch ), and comparing it to a programmable threshold ( rxvitthresholdxx ) with respect to the puncturing rate used for the depuncturing block. this rate is programmable (rxvitrate) in manual or semiautomatic mode, or searched automatically in automatic mode. if the error number is greater than the threshold, there is no synchronization, and synchrobit goes one state ahead in its state machine. there are several states for each puncturing rate since synchrobit is also in charge of resolving p /2 phase shift ambiguities as well as the ambiguity whether the depuncturing process starts in the right phase. an interrupt is generated at the end of the averaging period ( sbte) if the error number is greater than the threshold. when the synchro bit is found (interrupt sbf ), which happens when the error number is lower than the threshold, the search for a synchronization word (either 47h or its complemented value b8h for dvbs standard) starts in the synchroframe block. however, the frame synchronization may not happen on the first synchro word found, since 47h or b8h may simply be a useful data in the stream. rxsyncwctl register is used to program the number of consecutive synchro words encountered at the right place (every n bytes, where n is the frame length programmed in rxrsframel ) needed to confirm and synchronize the decoder, allowing 0, 1 or 2 mismatching bits in the oconfirmingo words (rxsyncwctl). in the same way, the desynchronization conditions can be programmed in rxdesyncwctl register: the number of consecutive nonsynchro words found every n bytes to desynchronize the decoder, and the number of error bits allowed. moreover, rxsyncwctl register also contains a programmable time out value representing the maximum duration of the synchro word research after viterbi synchro bit is found. if so, an interrupt is generated: tio . it has to be noticed that too many errors in reedsolomon decoder and in the descrambler can have the synchro frame desynchronize. these respective interrupts ( rssl and ddsc ) may be masked in rxdesyncwctl register. the interrupt indicating a synchro frame lock is lck . the one for a synchro frame loss is syl . all interrupts can be read from registers rxvitrsint0 and rxvitrsint1 . the deinterleaver block starts operating at reception of a synchro word coming from synchroframe. the reedsolomon decoder is able to correct up to 8 bytes. if reedsolomon detects more than 8 error bytes, it does not correct the error frame and it raises an error flag (interrupt rser ). after a certain number of consecutive error frames (programmable in the rxrsdesyncfn register), reedsolomon is said to be desynchronized (interrupt rssl), and may ask the synchroframe to start another synchronization search. due to reedsolomon encoding, each transmitted frame contains 16 check symbols in addition to the useful data. the descrambler is in charge of separating the useful data from rs check symbols. the burstsyncout signal is used to indicate the valid data. since the descrambler simulates the process of energy dispersal within transport packets, it looks for b8h synchro words to start operating. however, it outputs only 47h synchro words at the beginning of each frame. if it does not find a b8h synchro word at the expected place, it sets the interrupt ddsc to warn the synchro frame block that it is desynchronized. tss902e 10 mhs rev. d april 1999 5. register mapping and description 5.1. register mapping the following control and status registers purpose is to synchronize the viterbi decoder onto the right phase and puncturing rate as well as to monitor and tune the data stream quality and parameters. table 5: address mapping address name access reset signal reset value 0x01 rxvitcontrol viterbi control r/w resetb 0x00 0x02 to 0x06 rxvitthreshold viterbi threshold r/w resetb 0x00 0x07 rxvitsearch viterbi averaging period r/w resetb 0x00 0x08 / 0x09 rxvitmonitor viterbi monitoring period r/w resetb 0x00 0x0a / 0x0b rxviterror viterbi error rate r resetb ,, restart & write to rxvit- monitor 0x00 0x0c / 0x0d rxviterrorsync viterbi synchro error r resetb & restart 0x00 0x0e rxvitrate depuncturing rate r/w resetb 0x01 0x0f rxvitfreqin viterbi input frequency r/w resetb 0x00 0x10 rxsyncword synchro word r/w resetb 0x47 0x11 rxsyncwctl synchro word control r/w resetb 0x01 0x12 rxdesyncwctl out of sync word control r/w resetb 0x01 0x13 rxsyncstat synchro / out of sync status r resetb & restart 0x00 0x14 rxvitsynccompword synchro complemented word r/w resetb 0x88 0x20 / 0x21 rxvitrsint interrupt status r resetb & read rxvitrsint 0x00 0x22 / 0x23 rxvitrsmask interrupt mask r/w resetb 0xff / 0x3f 0x24 rxvitstatus viterbi status r resetb & restart 0x00 0x30 rxrsframel reed solomon frame length r/w resetb 0xcc 0x31 / 0x32 rxrserror reed solomon bit error count r resetb & restart 0x00 0x33 rxrsuncorrect rs uncorrected frame count r resetb & read rxrsuncorrect 0x00 0x34 rxrsframenb reed solomon max frame count r/w resetb 0x00 0x35 rxrsdesyncfn reed solomon out of sync frame r/w resetb 0x1f 0x40 rxrsvitact viterbi & rs activity control r/w resetb 0xff tss902e 11 mhs rev. d april 1999 5.2. register description 5.2.1. viterbi control rxvitcontrol register address = 0x01 reset value = 0x00 76543210 burstm a/m fre rst sec s/o psk h/s h/s hard/soft mode: 0 = soft decision (3 bits detection); 1 = hard decision using iext and qext msb only. psk modulation mode: 0 = qpsk (two inputs: iext and qext); 1 = bpsk (iext single input) secs/o: 00 = offset sign magnitude ; 01 = offset binary 10 = two's complement 11 = unused rst software reset: 0 = inactive; 1 = allows the device to restart the synchronization phase a/m & fre automatic / manual and freeze flags: a/m = 0 & fre = 0: automatic mode. successive enabled code rates are tried with all possible phases, until the system is locked and the block synchro is found; this is the default setup (reset mode). a/m = 0 & fre = 1: the code rate is frozen; if no synchro is found, the phase is swept but not the code rate. a/m = 1: manual mode. the system is forced to a code rate (that you have previously defined), ignoring the timeout register and the ber value. in this mode, each frebit 0 to 1 transition increments the phase, allowing full control of the synchronization by an external microcontroller, keeping the tuning giving the lowest ber. burstm burst mode: 0 = inactive (default); 1 = active. tss902e 12 mhs rev. d april 1999 5.2.2. viterbi threshold rxvitthreshold12 ra[7:0] register address = 0x02 reset value = 0x00 rxvitthreshold23 rb[7:0] register address = 0x03 reset value = 0x00 rxvitthreshold34 rc[7:0] register address = 0x04 reset value = 0x00 rxvitthreshold56 rd[7:0] register address = 0x05 reset value = 0x00 rxvitthreshold78 re[7:0] register address = 0x06 reset value = 0x00 76543210 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 re7 re6 re5 re4 re3 re2 re1 re0 ra [7:0], rb [7:0], rc [7:0], rd [7:0], re [7:0] bit error rate threshold: within each register, bits 7 to 0 represent a ber threshold (the average number of errors occuring during an averaging period). the current ber is compared to this programmable threshold. if it is greater, another phase (or another rate) is tried until th e proper rate is found (viterbi is synchronized). maximum threshold values: sn [5:0] = 1xxxxx => threshold = rx[7:0] & o0000000o. .128 > 32640 sn [5:0] = 01xxxx => threshold = rx[7:0] & o000000o . . . 64 > 16320 sn [5:0] = 001xxx => threshold = rx[7:0] & o00000o . . . . 32 > 8160 sn [5:0] = 0001xx => threshold = rx[7:0] & o0000o . . . . . 16 > 4080 sn [5:0] = 00001x => threshold = rx[7:0] & o000o . . . . . . . 8 > 2040 sn [5:0] = 00000x => threshold = rx[7:0] & o00o . . . . . . . . 4 > 1020 note: sn[5:0] word purpose is described in the rxvitsearch register paragraph. rx[7:0] & o00o means that two zeros are appended to the register value, giving for this example a minimum and a maximum thresho ld values of 4 (r[7:0] = 0x01) and 1020 (r[7:0] = 0xff). rx[7:0] stands for ra[7:0] to re[7:0]. tss902e 13 mhs rev. d april 1999 5.2.3. viterbi search rxvitsearch register address = 0x07 reset value = 0x00 76543210 0 0 sn5 sn4 sn3 sn2 sn1 sn0 sn [5:0] averaging period: the averaging period register defines the number of incoming bits used by the device to calculate the ber. 0x3f > 64k bits required to calculate the ber 0x3e > 63k bits required to calculate the ber ... ... 0x02 > 3k bits required to calculate the ber 0x01 > 2k bits required to calculate the ber 0x00 > 1k bits required to calculate the ber 5.2.4. viterbi monitoring rxvitmonitor0 register address = 0x08 reset value = 0x00 76543210 nb7 nb6 nb5 nb4 nb3 nb2 nb1 nb0 rxvitmonitor1 register address = 0x09 reset value = 0x00 0 0 nb13 nb12 nb11 nb10 nb9 nb8 nb [13:0] monitoring period: the monitoring period register defines the number of incoming bits required for ber statistical calculation done by the user . this value is a multiple of 1kbits. writing into this register starts a new monitoring period. at the end of this period, an in terrupt may be generated (if enabled by the rxvitrsmask1 register memp bit). 0x3fff > 16384k bits required to calculate the ber 0x3ffe > 16383k bits required to calculate the ber ... ... 0x0002 > 3k bits required to calculate the ber 0x0001 > 2k bits required to calculate the ber 0x0000 > 1k bits required to calculate the ber tss902e 14 mhs rev. d april 1999 5.2.5. viterbi error rate (read only) rxviterrormsb register address = 0x0a reset value = 0x00 76543210 erv15 erv14 erv13 erv12 erv11 erv10 erv9 erv8 rxviterrorlsb register address = 0x0b reset value = 0x00 erv7 erv6 erv5 erv4 erv3 erv2 erv1 erv0 erv [15:0] number of error bits: this 16bits counter gives the number of error bits found along a monitoring period. it may be used for an offline ber calculation done by the user. whenever a monitoring period completes, this counter is frozen; it is reset to zero when a monitoring period starts. 5.2.6. viterbi error synchro (read only) rxviterrorsync0 register address = 0x0c reset value = 0x00 76543210 ers7 ers6 ers5 ers4 ers3 ers2 ers1 ers0 rxviterrorsync1 register address = 0x0d reset value = 0x00 0 0 ers13 ers12 ers11 ers10 ers9 ers8 ers [13:0] number of incoming bits: this 14bits counter gives the number of kbits received during a monitoring period before the ber value reaches the ber threshold (leading to a synchronization loss). it may be used to locate the context in which the synchronization loss occurred. in conjunction with the rxviterror register, it may also be used to tune the ber threshold. 5.2.7. code rate rxvitrate register address = 0x0e reset value = 0x00 76543210 pbfrz pbrst 0 e4 e3 e2 e1 e0 e [4:0] enable code rate: this field sets the viterbi decoder code rate when working in manual mode or semiautomatic mode . 0x01 > code rate = 1/2 0x02 > code rate = 2/3 0x04 > code rate = 3/4 0x08 > code rate = 5/6 0x10 > code rate = 7/8 only one bit should be set to 1. any other e[4:0] contents leads to a 1/2 code rate selection. tss902e 15 mhs rev. d april 1999 pbrst : burst mode depuncturing restart bit: 0 = the incoming iext/qext data stream is continuously depunctured even if burstsyncin input pin is held to zero. 1 = stops the depuncturing process whenever burstsyncin input pin is set to zero (no valid burst data) and restarts on a ai/bj pair supposed to be the a1/b1 one. see the burst mode functional description. pbfrz : burst mode depuncturing freeze bit: 0 = the incoming iext/qext data stream is continuously depunctured even if burstsyncin input pin is held to zero. 1 = stops the depuncturing process whenever burstsyncin input pin is set to zero (no valid burst data) and restarts where it stopped. see the burst mode functional description. 5.2.8. viterbi input frequency rxvitfreqin register address = 0x0f reset value = 0x00 76543210 vcoc freq6 freq5 freq4 freq3 freq2 freq1 freq0 freq [6:0] pll external dividervalue in bpsk mode: freq [6:0] pll external dividervalue in qpsk mode: finbit : input frequency on ckbitext input pin: in automatic mode the default value should be: vcoc = 0 vcoc vco control: this bit determines the pll vco to be used 0 = vco2 is selected (output frequency range: 40 mhz to 130 mhz) 1 = vco1 is selected (output frequency range: 130 mhz to 230 mhz) 5.2.9. synchro word rxsyncword register address = 0x10 reset value = 0x47 76543210 syw7 syw6 syw5 syw4 syw3 syw2 syw1 syw0 syw [7:0] synchronization word: this register sets the synchronization word recognized by the viterbi module during synchro and lock phases. the viterbi synchronization module looks for syw [7:0] and its complemented value every scwth block (see rxvitsynccompword register). tss902e 16 mhs rev. d april 1999 5.2.10. synchro word control rxsyncwctl register address = 0x11 reset value = 0x01 76543210 tov1 tov0 0 msy1 msy0 sy2 sy1 sy0 sy [2:0] number of consecutive synchronization words: sy [2:0] is the number of consecutive synchronization words to be found to synchronize the decoder. msy [1:0] maximum number of mismatching bits: msy [1:0] is the maximum number of mismatching bits allowed to declare a match when comparing data stream to the expected synchronization word. (0, 1 or 2 mismatching bits maximum. if msy = 11, the number of allowed mismatching bits is set to 0). tov [1:0] time out value: the time out value programs the maximum duration of the synchronization word search after viterbi synchro bit is found. if no synchronization word is found within this duration, an interrupt is generated and the external system must change parameter s like the ber threshold or the msy value. 11 = time out (bit period) = 8 x scw [3:0] (see rxvitsynccompword register for scw[3:0] definition). 10 = time out (bit period) = 4 x scw [3:0] 01 = time out (bit period) = 3 x scw [3:0] 00 = time out (bit period) = 2 x scw [3:0] 5.2.11. loss of sync word control rxdesyncwctl register address = 0x12 reset value = 0x01 76543210 drsm dscm 0 mds1 mds0 dsy2 dsy1 dsy0 dsy [2:0] number of consecutive lost synchronization words: dsy [2:0] is the number of consecutive not expected synchronization words required to go out of sync. mds [1:0] maximum number of mismatching bits: mds [1:0] is the maximum number of mismatching bits allowed to declare a match when comparing data stream to the expected synchronization word (0, 1 or 2 bits maximum. if mds = 11 the number of mismatching bits is set to 0). dscm descrambler out of sync mask: 0 = descrambler out of sync unmasked; 1 = descrambler out of sync masked drsm reedsolomon out of sync mask: 0 = reed solomon out of sync unmasked; 1 = reed solomon out of sync masked 5.2.12. synchro / out of sync status (read only) rxsyncstat register address = 0x13 reset value = 0x00 76543210 dsw3 dsw2 dsw1 dsw0 dsv3 dsv2 dsv1 dsv0 dsv [3:0] number of out of sync bits: dsv [3:0] is a counter incremented each time the viterbi looses sync after the first lock. dsw [3:0] number of out of sync words: dsw [3:0] is a counter incremented each time the synchronization word mechanism looses sync after the first lock. tss902e 17 mhs rev. d april 1999 5.2.13. complemented syncword rxvitsynccompword register address = 0x14 reset value = 0x88 76543210 cena sapi 0 0 scw3 scw2 scw1 scw0 scw [3:0] complemented synchro word position: the complemented synchro word periodically appears after scw frames. sapi correct pi ambiguity in burst mode: 0 = no correction; 1 = p ambiguity correction enabled in burst mode cena complemented sync word reseach enable: 0 = complemented sync word search disabled; 1 = complemented sync word search enabled. 5.2.14. interrupt status (read only) rxvitrsint0 register address = 0x20 reset value = 0x00 76543210 odfc tio sbf lck syl rssl rser tebrs rxvitrsint1 register address = 0x21 reset value = 0x00 76543210 0 0 ddsc odbc sbte eap meco emp tebrs reedsolomon monitoring period finished rser reedsolomon found more than 9 bytes in error rssl reedsolomon out of sync syl synchro lost lck synchro word found sbf synchro bit found tio time out period without finding synchro word odfc overflow out of sync frame counter emp viterbi monitoring period finished meco monitoring errors counter overflow eap viterbi averaging period finished sbte synchro bit threshold error odbc synchro bit lost counter overflow ddsc descrambler out of sync the above bits give information about the interrupt generation event. a bit set to 1 shows the interrupt origin. tss902e 18 mhs rev. d april 1999 5.2.15. interrupt mask rxvitrsmask0 register address = 0x22 reset value = 0xff 76543210 modfc mto mprf mlck msyl mrssl mrser mtebrs rxvitrsmask1 register address = 0x23 reset value = 0x3f 76543210 0 0 mdds modbc msbte meap mmeco memp mtebrs reedsolomon monitoring period finished mrser reedsolomon found more than 9 bytes in error mrssl reedsolomon out of sync msyl synchro lost mlck synchro word found mprf synchro bit found mto time out period without finding synchro word modfc overflow out of sync frame counter memp viterbi monitoring period finished mmeco monitoring errors counter overflow meap viterbi averaging period finished msbte synchro bit threshold error modbc synchro bit lost counter overflow mdds descrambler out of sync when set to 1, the above bits mask the corresponding interrupts. 5.2.16. viterbi status (read only) rxvitstatus register address = 0x24 reset value = 0x00 76543210 plu emp tio sbf lck pr2 pr1 pr0 pr [2:0] current code rate : in automatic mode, pr [2:0] indicates the current code rate according to the following table: 100 = code rate 7/8 011 = code rate 5/6 010 = code rate 3/4 001 = code rate 2/3 000 = code rate 1/2 lck synchro word found: 0 = searching for synchro word; 1 = synchro word found and locked . sbf synchro bit found: sbf indicates the code rate search status. this bit is irrelevant in manual mode. 0 = searching for synchro bit; 1 = synchro bit found and locked . tio time out period without swf: 0 = (see conditions for tio = 1) 1 = when synchro bit is found and no synchro word is found within the time out duration. emp viterbi end of monitoring period: tss902e 19 mhs rev. d april 1999 0 = monitoring period not finished. 1 = monitoring period finished. a write access to the rxvitmonitor registers resets this bit. plu pll lock/unlock: 0 = pll unlocked; 1 = pll locked . 5.2.17. reed solomon frame length rxrsframel register address = 0x30 reset value = 0xcc 76543210 fl7 fl6 fl5 fl4 fl3 fl2 fl1 fl0 fl [7:0] frame length: the reed solomon decoder is based on the original rs (255, 239, t = 8) code, and supports the following shortening k = 34 to 239. this also includes the dvb specification of rs (204, 188, t = 8). the default value is 204 (0xcc), and might be overwritte n by values from 50 (34 + 16) to 255 (239 + 16). 5.2.18. reedsolomon bit error count (read only) rxrserrlsb register address = 0x31 reset value = 0x00 76543210 e7 e6 e5 e4 e3 e2 e1 e0 rxrserrmsb register address = 0x32 reset value = 0x00 76543210 e15 e14 e13 e12 e11 e10 e9 e8 e [15:0] rs bit error count: e [15:0] stores the value of the rs bit error count used to calculate the reedsolomon ber. if there are more than 8 bytes on e rror in a frame, the bit error count is not incremented. if there are 8 bytes on error in a frame with 8 bits on error in each byte, the bit error count is not incremented; this is a bug that will be fixed in the next version. 5.2.19. reedsolomon uncorrected frames count (read only) rxrsuncorrect register address = 0x33 reset value = 0x00 76543210 unf7 unf6 unf5 unf4 unf3 unf2 unf1 unf0 unf [7:0] uncorrected frame number: unf [7:0] is the rs frame error counter used to calculate the reedsolomon ber. unf error count is incremented each time there are more than 8 bytes on error in a frame. tss902e 20 mhs rev. d april 1999 5.2.20. reed solomon maximum frame count rxrsframenb register address = 0x34 reset value = 0x00 76543210 fn7 fn6 fn5 fn4 fn3 fn2 fn1 fn0 fn [7:0] maximum frame count: fn [7:0] bits are the 8msb preset value of a 10bit counter used to define the rs monitoring period duration. at the end of th is time, the rxrserr and rxrsuncorrect registers are updated and an interrupt (tebrs) is generated. writing into this register starts a new rs monitoring period. 5.2.21. reedsolomon out of sync frame rxrsdesyncfn register address = 0x35 reset value = 0x1f 76543210 wer 0 0 drsy4 drsy3 drsy2 drsy1 drsy0 drsy [4:0] reedsolomon out of sync frame number: drsy[4:0] is the number of consecutive reedsolomon erroneous frames required to indicate sync loss. wer write error bit: 0 = data is not affected. 1 = if a noncorrectable error occurs, the otransport_error_indicatoro (msb of the first byte following the synchro byte) is forced to '1' after descrambling. tss902e 21 mhs rev. d april 1999 5.2.22. viterbi and reedsolomon activity control rxrsvitact register address = 0x40 reset value = 0xff 76543210 sybe ede rse die sye ve dpe plle plle pll enable: 0 = pll disabled, the clock rate equals external clock rate and the pll input clock pll is held low. 1 = pll enabled, the clock rate is generated by the pll. dpe depuncturing enable: 0 = data is not affected; 1 = input data stream is depunctured. ve viterbi enable: 0 = data is not affected; 1 = input data stream is corrected by the viterbi decoder. sye synchro enable: 0 = parallel data come from external pin (iext, qext, testiera, testqera). 1 = serial flow is converted to parallel data by synchro. die deinterleaver enable: 0 = data is not affected; 1 = input data stream is deinterleaved. rse reedsolomon enable: 0 = data is not affected; 1 = errors are corrected. ede energy dispersal removal enable: 0 = data is not affected; 1 = output data from rs is descrambled. sybe synchro bit enable: 0 = the synchro bit found is generated to allow other blocks to work (except viterbi decoder). 1 = the viterbi error processing is enabled. tss902e 22 mhs rev. d april 1999 6. signals descriptions and specifications 6.1. signals descriptions name active state or edge description microprocessor signals cs low chip select input. as edge address latch input. rdwrb low / high read (high) / write (low) signal. ad[7:0] address bus. dup[7:0] bidirectional data bus. resetb low reset. when active, forces all blocks into a known state. must be used as specified in the ac parameters section. irq low interrupt output. may be used by the external system for sync monitoring purpose. demodulator signals iext[2:0] 3bit soft decision input. use iext[2] for hard decision input. qext[2:0] 3bit soft decision input. use qext[2] for hard decision input. burstsyncin high burst mode control pin. when high, indicates an incoming data burst. when low, indicates irrelevant data on iext and qext pins in burst mode. pll signals ckbitext edge symbol clock for iext and qext. xxxoutf pll external rc filter connection. output signals dataout[7:0] data output bus. may be read on the ckoctout output clock rising edge. ckoctout edge parallel data output sampling signal. syncout high active whenever a frame sync word is found. frameout high active whenever a multiframe sync word is found. dataouts serial data output. may be read on the ckbitout output clock rising edge. ckbitout serial data output sampling signal. burstsyncout high active whenever a multiframe sync word is found; remains high for a frame length duration. test signals testiera depuncturing block i test input. testqera depuncturing block q test input. testckoct edge byteformat data test clock. testckoct90 edge byteformat data test clock (pi/2 delayed from testckoct). testsync high indicates a sync word occurrence. testckbit edge in test mode, emulates the depunctured data clock. testckbit90 edge in test mode, emulates the depunctured data clock (pi/2 delayed from testckbit). tss902e 23 mhs rev. d april 1999 name active state or edge description depuncturing signals iext[2:0] 3bit soft decision input. use iext[2] for hard decision input. qext[2:0] 3bit soft decision input. use qext[2] for hard decision input. burstsyncin high burst mode control pin. when high, indicates an incoming data burst. when low, indicates irrelevant data on iext and qext pins in burst mode. ckbitext edge symbol clock for iext and qext. testckbit edge in test mode without pll, emulates the depunctured data clock. dataout[7:5] represent iout[2:0] with added bits according to the code rate dataout[4:2] represent qout[2:0] with added bits according to the code rate dataout[1] when this output equal 1, iout are added bits (erasei) dataout[0] when this output equal 1, qout are added bits (eraseq) ckbitout serial data output sampling signal. viterbi signals iext[2:0] 3bit soft decision input (with or without added bits according to the usage of depuncturing block). use iext[2] for hard decision input. qext[2:0] 3bit soft decision input (with or without adding bits according to the usage of depuncturing block). use qext[2] for hard decision input. testiera high indicates the i adding bits if the depuncturing block is not used testqera high indicates the q adding bits if the depuncturing block is not used burstsyncin high if the depuncturing block is not used, the activity on this signal indicates an incoming data. otherwise it indicates irrelevant data on iext and qext pins. with the depuncturing block this signal value makes sense only if the burst mode is pro- grammed. testckbit edge witout pll, emulates the depunctured data clock. testckbit90 edge witout pll, emulates the depunctured data clock (pi/2 delayed from testckbit) ckbitext edge external clock bit needed if the depuncturing block is used. its frequency depends on the usage of the depuncturing block. dataout[0] viterbi serial output. ckbitout serial data output sampling signal. synchro_bit signals (without viterbi and depuncturing blocks) burstsyncin high when high, indicates an incoming data. testsync high when high, emulates a viterbi error. testckbit edge external clock bit needed if the pll is not used ckbitext edge external clock bit needed if the pll is used synchro_frame signals (without viterbi, depuncturing and synchro_bit blocks) iext[2] input serial data. testckbit edge external clock bit needed if the pll is not used ckbitext edge external clock bit needed if the pll is used burstsyncin high when high, indicates a valid incoming data in burst mode. testsync high when high, indicates an incoming data in burst mode. this signal must be set to one 6 bits before the real valid data and set to zero 6 bits before the burst end. dataout[7:0] parallel data output bus. may be read on the ckoctout output clock rising edge. dataouts serial data output. may be read on the ckbitout output clock rising edge. syncout high active whenever a frame sync word is found or during the first frame word in burst mode according to the frame length. burstsyncout high active whenever a synchroframe is locked or when dataout is valid in burst mode. tss902e 24 mhs rev. d april 1999 description active state or edge name ckoctout parallel data output sampling signal. ckbitout serial data output sampling signal. convolutional deinterleaver signals iext[2:0] input deinterleaver parallel data[7:5], iext[2] => input deinterleaver serial data if syn- chro_frame is used. qext[2:0] input deinterleaver parallel data[4:2] testiera input deinterleaver parallel data[1] testqera input deinterleaver parallel data[0] ckbitext edge external clock bit needed if the pll is not used testckbit edge external clock bit needed if the pll is used testckoct edge external clock byte needed if synchro_frame is not used testsync high emulates the input frame sync word if synchro_frame is not used dataout[7:0] parallel data output bus. may be read on the ckoctout output clock rising edge. dataouts serial data output. may be read on the ckbitout output clock rising edge. syncout high active whenever a frame sync word is transmitted to the output burstsyncout high active whenever a complete convolutional interleaving sequence is processed and all output data are valid ckoctout parallel data output sampling signal. ckbitout serial data output sampling signal. reedsolomon decoder signals iext[2:0] input reedsolomon parallel data[7:5], iext[2] => input reedsolomon serial data if syn- chro_frame is used. qext[2:0] input reedsolomon parallel data[4:2] testiera input reedsolomon parallel data[1] testqera input reedsolomon parallel data[0] ckbitext edge external clock bit needed if the pll is used and synchro_frame is used. testckbit edge external clock bit needed if the pll is not used and synchro_frame is used. testckoct edge external clock byte needed if synchro_frame is not used testckoct90 edge external clock byte needed if synchro_frame is not used (pi/2 delayed from testckoct) testsync high emulates the input frame sync word if synchro_frame is not used according to the frame lenght. burstsyncin high when high, indicates a valid incoming frame. dataout[7:0] parallel data output bus. may be read on the ckoctout output clock rising edge. dataouts serial data output. may be read on the ckbitout output clock rising edge only if an input clock bit is used. syncout active whenever a frame sync word is transmitted to the output burstsyncout when high, indicates a valid output frame. ckoctout parallel data output sampling signal. ckbitout serial data output sampling signal. descrambler signals iext[2:0] input descrambler parallel data[7:5], iext[2] => input descrambler serial data if syn- chro_frame is used. qext[2:0] input descrambler parallel data[4:2] testiera input descrambler parallel data[1] testqera input descrambler parallel data[0] tss902e 25 mhs rev. d april 1999 description active state or edge name ckbitext edge external clock bit needed if the pll is used and synchro_frame is used. testckbit edge external clock bit needed if the pll is not used and synchro_frame is used. testckoct edge external clock byte needed if synchro_frame is not used testsync high emulates the input frame sync word if synchro_frame is not used according to the frame lenght. dataout[7:0] parallel data output bus. may be read on the ckoctout output clock rising edge. dataouts serial data output. may be read on the ckbitout output clock rising edge only if an input clock bit is used. syncout high active whenever a frame sync word is transmitted to the output burstsyncout high active whenever a multiframe sync word is found; remains high for a frame length duration without reedsolomon syndrome (active during 188 byte) . frameout high active whenever a multiframe sync word is found. ckoctout parallel data output sampling signal. ckbitout serial data output sampling signal. tss902e 26 mhs rev. d april 1999 6.2. pinout description tss902e 27 mhs rev. d april 1999 7. programming and operation modes this chapter describes how to operate the tss902e from the programmer's point of view. most of the tss902e registers are made of several fields. in the following descriptions, the concerned registers and fields names will be mentioned as well as recommended values. you should read the register description section anyway since some registers particularities like unvalid registers values are not covered in this chapter. 7.1. device activity control in order to give great flexibility to a system designer, each functional block may be bypassed. you will probably start the tss902e setup by enabling the blocks you want to be activated. the following sections show how to configure the device in order to activate some blocks only, or the whole circuit. 7.1.1. using the viterbi decoder only working with the viterbi decoder only requires three conditions: the rate is 1/2; i.e. there is no data puncturing. qpsk mode is used when running in bpsk mode, the i/q data stream coming to the iext pins with the i1 q1 i2 q2 i3 q3 sequence is demultiplexed by the depuncturing block; consequently, using the bpsk mode requires the depunctur- ing block to be enabled. for the viterbi decoder to run alone properly, you must be able to provide it with two stable clock signals. if you can not guarantee the clocks stability, you must use the depuncturing block which compensates the clocks jitter. viterbi decoder iext(2:0) qext(1:0) testckbit testckbit90 dataout(0) ckbitout iext/qext data is clocked on the testckbit rising edge; there is a pi/2 phase delay between testckbit and testckbit90. the others device pins must be set as follows: testiera, testqera and testsync connected to vss (ground). ckbitext, testckoct and testckoct90 connected to vcc. rxrsvitact register = 0x84 tss902e 28 mhs rev. d april 1999 7.1.2. using the viterbi decoder and the depuncturing block without pll viterbi decoder & depuncturing iext(2:0) qext(1:0) testckbit testckbit90 dataout(0) ckbitout ckbitext the ckbitext clock is the iext and qext symbols clock. these signals timing relationship is shown in section 8.6. the testckbit clock frequency depends on the bpsk/qpsk mode and the puncturing rate as follows: bpsk testckbit_freq = ckbitext_freq x punct_rate if punct_rate = 1/2, you must generate a testckbit clock with a frequency of half the ckbitext one. in bpsk mode, the data stream comes on iext(2:0) pins only; the qext(2:0) must be connected to ground. qpsk testckbit_freq = ckbitext_freq x punct_rate x 2 if punct_rate = 1/2, testckbit_freq = ckbitext_freq the testckbit90 clock frequency is the same than the testckbit one; there is only a pi/2 phase shift between them. the others device pins must be set as follows: testiera, testqera and testsync connected to vss (ground). testckoct and testckoct90 connected to vcc. rxrsvitact register = 0x86 tss902e 29 mhs rev. d april 1999 7.1.3. using the viterbi decoder and the depuncturing block with pll using the tss902e with its pll is much more simple since you do not need to generate the testckbit and testckbit90 clocks. viterbi decoder & depuncturing & pll iext(2:0) qext(1:0) dataout(0) ckbitout ckbitext the ckbitext clock is the iext and qext symbols clock. these signals timing relationship is shown in section 8.6. the others device pins must be set as follows: testiera, testqera and testsync connected to vss (ground). testckoct, testckoct90, testckbit and testckbit90 connected to vcc. rxrsvitact register = 0x87 7.1.4. using the reed solomon decoder only reed solomon decoder iext(2:0) qext(1:0) testiera testqera testckoct testckoct90 testsync the reedsolomon decoder input data stream is made of 8bit parallel data coming on (from msb to lsb): iext(2:0), qext(2:0), testiera and testqera pins. the data stream is clocked on testckoct rising edge; there is a pi/2 phase delay between testckoct and testckoct90 clocks. the testsync signal must be supplied to mark each sync byte occurence. 7.2. setting the sync and sync loss criterions we address here the programming of the rxsyncwctl and rxdesyncwctl registers. the most important function for the evaluation of data from the mpeg2 transport stream (ts) is the sync tss902e 30 mhs rev. d april 1999 acquisition. the actual synchronization of the ts depends on the number of correct sync bytes necessary for the device to synchronize and on the number of distorded sync bytes which the device can not cope with. five consecutive correct sync bytes are usually considered as sufficient for sync acquisition and two or more consecutive corrupted sync bytes should indicate sync loss. rxsyncwctl sy[2:0] = 5 rxdesyncwctl dsy[2:0] = 2 mismatching bits are allowed during the sync bytes search; you can define the maximum allowed number of mismatching bits when comparing the data stream to the expected sync byte. let us take an example: the expected sync byte is 0x47; if you allow one mismatching bit, then the following bytes will be considered as valid sync bytes: 0x46, 0x45, 0x43, 0x4f, 0x57, 0x67, 0x07 and 0x97. although you can set the number of mismatching bits to 0, 1 or 2, it is recommended to set it to zero so that the device does not get synced on wrong data. rxsyncwctl msy[1:0] = 0 once the frame sync is got, the device may loose it whenever the expected sync byte can not be found. a mismatching bits mechanism also exists for sync loss conditions. let us suppose that we expect a 0x47 value as sync byte. if the device reads 0x46, it will consider it as a valid sync byte if you have set the number of allowed mismatching bits to one. in that case, the device will remain synced. a value of one is a good tradeoff for sync loss conditions. rxdesyncwctl mds[1:0] = 1 a time out value may be defined to program the maximum duration of the sync word search after the bit sync is found. once the time out duration is elapsed, an interrupt is generated and the bit sync state machine goes one step beyond. the interrupt may be used by the external system to change the ber threshold, for example. this parameter is not significant for the device to synchronize properly. rxsyncwctl tov[1:0] = 0 we can now summarize these registers setup with: rxsyncwctl = 0x05 rxdesyncwctl = 0x0a tss902e 31 mhs rev. d april 1999 8. ac characteristics 8.1. reset timing parameter / event definition min max units trstlrsth resetb minimum pulse width 10 usec the resetb signal is asynchronous. 8.2. microprocessor write timing parameter / event definition min max units tadvasl address setup to as low 5 nsec tasladx address hold from as low 5 nsec tcslcsh chip select minimum pulse width 20 nsec twlwh write signal minimum pulse width 20 nsec tdvwh data setup to end of write (cs high or rdwrb high) 10 nsec twhdx data hold from end of write (cs high or rdwrb high) nsec the device internal write condition is: cs low and rdwrb low. tss902e 32 mhs rev. d april 1999 8.3. microprocessor read timing parameter / event definition min max units tadvasl address setup to as low 5 nsec tasladx address hold from as low 5 nsec tcslcsh chip select minimum pulse width 20 nsec trhrl read signal minimum pulse width 20 nsec trhdv read start to output valid 40 nsec tcshdx end of read to invalid output nsec trldz end of read to high impedance nsec the device internal read condition is: cs low and rdwrb high. 8.4. microprocessor data bus interface in systems in which the tss902e dup data bus is shared with others devices, it is mandatory to isolate the tss902e dup bus by inserting an octal bidirectional buffer between the device dup bus and the external system microcontroller data bus, as shown in the following figure: system data bus dup (7:0) cs rdwrb cs rdwrb tss902e tss902e 33 mhs rev. d april 1999 8.5. interrupt timing after irq output goes down, the microcontroller starts the interrupt registers read operation ( rxvitrsint0 & rxvitrsint1 ) in order to find the interrupt origin. both registers contents must be read and stored; reading these registers clears them. as long as these registers remain uncleared, the irq signal stays at low level. a cs rising edge transition indicates an end of read. two ckbitout rising edges after end of read, the irq signal returns to high level. the microcontroller must guarantee 4 clock periods between two interrupt registers reading. 8.6. iext[2:0] and qext[2:0] inputs timing parameter / event definition min max units tiqvcklh iext & qext setup to ckbitext high 5 nsec tcklhiqx iext & qext hold from ckbitext high 5 nsec 8.7. outputs timing parameter / event definition min max units tckdata delay from ckoctout clock falling edge to dataout. 5 nsec tcksyncout delay from ckoctout clock falling edge to syncout. 5 tckframeout delay from ckoctout clock falling edge to frameout. 5 tckburstout delay from ckoctout clock falling edge to burstsyncout. 5 tckdatas delay from ckbitout clock falling edge to dataouts. 5 nsec tss902e 34 mhs rev. d april 1999 8.8. pll block pll block functionality requirements: enable the pll block by setting the rxrsvitact register plle bit. the rxvitfreqin register freq[6:0] and vcoc bits must be set as explained in the registers section. the code rate must be defined through the rxvitrate register and the manual mode must be selected through the rxvitcontrol one. the above timing diagram requires freq[6:0] to be set to 00h and vcoc to 0; the code rate is 3/4 ( rxvitrate = 04h). the internally generated depuncturing clock can be observed at the ckbitout pin. tss902e 35 mhs rev. d april 1999 8.9. depuncturing block parameter / event definition min max units tckbersiqh delay from testckbit clock falling edge to erasei/eraseq rising edge. 20 nsec tckbersiql delay from testckbit clock falling edge to erasei/eraseq falling edge. 20 nsec tckbdoutv delay from testckbit clock falling edge to depunctured output data valid. 20 nsec tckbckout delay from testckbit clock falling edge to ckbitout falling edge. nsec depuncturing block test requirements: enable the depuncturing block by setting the rxrsvitact register dpe bit. the code rate must be defined through the rxvitrate register and the manual mode must be selected through the rxvitcontrol one. if the code rate is different to 1/2 the synchrobit must be enable (set sybe ) the testckbit clock frequency and phase must be set properly, according to the selected code rate. in the above timing diagram the depuncturing rate is 3/4 (rxvitrate = 04h). tss902e 36 mhs rev. d april 1999 the above timing diagram shows a depuncturing block test sequence using a 7/8 rate. tss902e 37 mhs rev. d april 1999 8.10. viterbi decoder viterbi decoder test requirements: enable the viterbi decoder by setting the rxrsvitact register ve bit. in the above sequence, we assume that a 3/4 code rate is used; the incoming data is already depunctured and sequenced by the testckbit clock. the testiera and testqera inputs must be controlled accordingly to the 3/4 rate. in viterbi test mode, the decoded bits can be found on dataout(0) or dataouts outputs after 290 testckbit clock periods (the viterbi decoder latency). the ckbitout output clock must be checked. an other possible viterbi test sequence is to feed iext and qext with data of code rate 1/2 (no puncturing); in that case, the testiera and testqera inputs must be held low continuously. tss902e 38 mhs rev. d april 1999 8.11. synchroframe block synchroframe block test requirements: enable the synchroframe block by setting the rxrsvitact register sye bit. in the above timing diagram, the incoming data onto iext(2) is supposed to be the viterbi decoder output, clocked by the testckbit signal. the rxrsframel register is set to its default hexadecimal cc value (a 204 bytes frame length). the rxsyncword register is set to its default hexadecimal 47 value. the output data can be read onto dataout(7:0) on ckoctout clock falling edge. the syncout signal goes high whenever the sync word is found. the burstsyncout signal goes high and remains high as long as the sync word is found. tss902e 39 mhs rev. d april 1999 8.12. deinterleaver block deinterleaver block test requirements: enable the deinterleaver block by setting the rxrsvitact register die bit. in the above timing diagram, the incoming data fromsyncframe(7:0) is supposed to be the synchroframe block output and must be valid on the testckoct clock falling edge. in test mode, fromsyncframe(7:0) is made, from msb to lsb of: iext(2:0), qext(2:0), testiera and testqera. there is a pi/2 delay between testckoct and testckoct90 clocks. the rxrsframel register is set to its default hexadecimal cc value (a 204 bytes frame length). the rxsyncword register is set to its default hexadecimal 47 value. the testsyncin input must be high whenever the sync byte is present onto the input bus. if sync words periodically appear into the input data stream, the burstsyncin input must be kept high. the output data can be read onto dataout(7:0) on ckoctout clock falling edge after the deinterleaver block latency (1280 testckoct clock periods). the output data may also be read onto the dataouts serial output on ckbitout falling edge. tss902e 40 mhs rev. d april 1999 8.13. reedsolomon decoder reedsolomon decoder test requirements: enable the reedsolomon block by setting the rxrsvitact register rse bit. in the above timing diagram, the incoming data fromdeinterleaver(7:0) is supposed to be the deinterleaver block output and must be valid on the testckoct clock falling edge. in test mode, fromdeinterleaver(7:0) is made, from msb to lsb of: iext(2:0), qext(2:0), testiera and testqera. there is a pi/2 delay between testckoct and testckoct90 clocks. the rxrsframel register is set to its default hexadecimal cc value (a 204 bytes frame length). the rxsyncword register is set to its default hexadecimal 47 value. the testsyncin input must be high whenever the sync byte is present onto the input bus. if sync words periodically appear into the input data stream, the burstsyncin input must be kept high. the output data can be read onto dataout(7:0) on ckoctout clock falling edge after the reedsolomon decoder latency (2 x framelength + 50bytes). tss902e 41 mhs rev. d april 1999 8.14. descrambler block descrambler block test requirements: enable the descrambler block by setting the rxrsvitact register ede bit. in the above timing diagram, the incoming data fromreedsolomon(7:0) is supposed to be the reedsolomon decoder output and must be valid on the testckoct clock falling edge. in test mode, fromreedsolomon(7:0) is made, from msb to lsb of: iext(2:0), qext(2:0), testiera and testqera. there is a pi/2 delay between testckoct and testckoct90 clocks. the rxrsframel register is set to its default hexadecimal cc value (a 204 bytes frame length). the rxsyncword register is set to its default hexadecimal 47 value. the testsyncin input must be high whenever the sync byte or its complemented value are present onto the input bus. if sync words periodically appear into the input data stream, the burstsyncin input must be kept high. the output data can be read onto dataout(7:0) on ckoctout clock falling edge after the descrambler block latency (half a testckoct period). the burstsyncout signal goes high on b8h occurence and remains high for a 188 bytes duration. tss902e 42 mhs rev. d april 1999 9. absolute maximum rating and operating conditions 9.1. absolute maximum rating table 6: absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . voltage on any other pin to vss . . . . . . . . . . . i ol per i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation . . . . . . . . . . . . . . . . . . . . . . 65 to +150 c 0.5 to +6.5 v 3 w 9.2. operating conditions table 7: operating conditions ambient temperature under bias space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vdd high speed versions . . . . . . . . . . . . . . . . . . . . . 55 to +125 c 55 to +125 c 4.5 to 5.5 v note: stressing the device beyond the aabsolute maximum ratingso may cause permanent damage. these are stress ratings only. operation beyond the aoperating conditionso is not recommended and extended exposure beyond the aoperating conditionso may affect device reliability . tss902e 43 mhs rev. d april 1999 10. dc characteristics space and military ranges table 8: dc characteristics at 5v +10%, t a = 55 to +125 c symbol parameter min typical max units test conditions v il input low voltage 0.5 0.2vdd - 0.1 v v ih input high voltage 0.2vdd + 0.9 vdd + 0.5 v v ol output low voltage 0.4 0.4 v i ol = 3 ma i ol = 6 ma v oh output high voltage 2.4 v i oh = 10 m a i il input leakage current no pullup/pulldown with pullup with pulldown 50 +/ 5 +360 m a i oz 3state output leakage current +/ 1 +/ 5 m a o p eratin g current iccop operating current viterbi block 20.5 ma/mhz reedsolomon block 2.2 iccsb standby current 20 ma tss902e 44 mhs rev. d april 1999 package mm inch figure 2: 132 pins mqfpf tss902e 45 mhs rev. d april 1999 ordering information ts s 902e s a /883 temic semiconductors ts part number 902 e: radiation tolerant z: depuncturing and viterbi decoder option (without pll) temperature range m: military 55 c to +125 c s: space 55 c to +125 c packaging a: mqfp 132 pins b: die flow e: engineering sample blank: standard military /883: mil 883 compliant b or s p883: mil 883 compliant b+ pind test sb: scc9000 level b sc: scc9000 level c sl3: lat3 sl2: lat2 sl1: lat1 hxxx: customer code (e mil. temperature) product line s: assp example : tss902e s a /883 france yyww lot nb the information contained herein is subject to change without notice. no responsibility is assumed by temic for using this publ ication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result fro m its use. |
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